InfoCoBuild

Advanced VLSI Design

Advanced VLSI Design. Instructors: Prof. A. N. Chandorkar, Prof. D. K. Sharma, Prof. Sachin Patkar, and Prof. Virendra K. Singh, Department of Electrical Engineering, IIT Bombay. This course covers topics in VLSI design: Historical perspective of VLSI, CMOS VLSI design for power and speed consideration, Logical effort, Designing fast CMOS circuits, Datapath design, Interconnect aware design, Hardware description Languages for VLSI design, FSM controller/datapath and processor design, VLSI design automation, and VLSI design test and verification. (from nptel.ac.in)

Lecture 15 - Interconnect Aware Design: Low Swing and Current Mode Signaling


Go to the Course Home or watch other lectures:

Lecture 01 - Historical Perspective and Future Trends in CMOS VLSI Circuit and System Design
Lecture 02 - Historical Perspective and Future Trends in CMOS VLSI Circuit and System Design (cont.)
Lecture 03 - Logical Effort - A Way of Designing Fast CMOS Circuits
Lecture 04 - Logical Effort - A Way of Designing Fast CMOS Circuits (cont.)
Lecture 05 - Logical Effort - A Way of Designing Fast CMOS Circuits (cont.)
Lecture 06 - Power Estimation and Control in CMOS VLSI Circuits
Lecture 07 - Power Estimation and Control in CMOS VLSI Circuits (cont.)
Lecture 08 - Low Power Design Techniques
Lecture 09 - Low Power Design Techniques (cont.)
Lecture 10 - Arithmetic Implementation Strategies for VLSI
Lecture 11 - Arithmetic Implementation Strategies for VLSI (cont.)
Lecture 12 - Arithmetic Implementation Strategies for VLSI (cont.)
Lecture 13 - Arithmetic Implementation Strategies for VLSI (cont.)
Lecture 14 - Interconnect Aware Design: Impact of Scaling, Buffer Insertion and Inductive Peaking
Lecture 15 - Interconnect Aware Design: Low Swing and Current Mode Signaling
Lecture 16 - Interconnect Aware Design: Capacitively Coupled Interconnects
Lecture 17 - Introduction to Hardware Description Languages
Lecture 18 - Managing Concurrency and Time in Hardware Description Languages
Lecture 19 - Introduction to VHDL
Lecture 20 - Basic Components in VHDL
Lecture 21 - Structural Description in VHDL
Lecture 22 - Behavioral Description in VHDL
Lecture 23 - Introduction to Verilog
Lecture 24 - Finite State Machine + Datapath (GCD Example)
Lecture 25 - FSM + Datapath (cont.)
Lecture 26 - Single cycle MMIPS
Lecture 27 - Multicycle MMIPS
Lecture 28 - Multicycle MMIPS? FSM
Lecture 29 - Brief Overview of Basic VLSI Design Automation Concepts
Lecture 30 - Netlist and System Partitioning
Lecture 31 - Timing Analysis in the Context of Physical Design Automation
Lecture 32 - Placement Algorithm
Lecture 33 - Introduction to VLSI Testing
Lecture 34 - VLSI Test Basics
Lecture 35 - VLSI Test Basics (cont.)
Lecture 36 - VLSI Testing: Automatic Test Pattern Generation
Lecture 37 - VLSI Testing: Design for Test
Lecture 38 - VLSI Testing: Built-In-Self Test
Lecture 39 - VLSI Design Verification: An Introduction
Lecture 40 - VLSI Design Verification (cont.)
Lecture 41 - VLSI Design Verification: Equivalence/Model Checking
Lecture 42 - VLSI Design Verification: Model Checking