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Digital Circuits and Systems

Digital Circuits and Systems. Instructor: Prof. Shankar Balachandran, Department of Computer Science and Engineering, IIT Madras. Digital circuits are the basic blocks of modern electronic devices like mobile phones, digital cameras, microprocessors and several other devices. In this course, we will learn the fundamentals of digital circuits and how to engineer the building blocks that go into digital subsystems. We will learn the basics of combinational as well as sequential logic. We will also have a thorough treatment of sequential circuits and state machines. We will also learn how to analyze the performance of digital circuits. The course will emphasize on the design philosophy as well as good design practices used. Students will also get an exposure to Verilog, a popular hardware modeling language. (from nptel.ac.in)

Lecture 30 - State Machines: FSM Design Problems

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Lecture 01 - Introduction

Lecture 02 - Basic Boolean Logic

Lecture 03 - Boolean Theorems

Lecture 04 - Minterms, Maxterms, Sum of Products (SOP), Products of Sum (POS)

Lecture 05 - Algebraic Minimization Examples

Lecture 06 - Introduction to Verilog

Lecture 07 - Universality, Rearranging Truth Tables

Lecture 08 - Karnaugh Maps

Lecture 09 - K-Map Minimization

Lecture 10 - K-Map with Don't Cares

Lecture 11 - Minimization of Multiple Output Functions

Lecture 12 - Number Systems

Lecture 13 - Encoders and Decoders

Lecture 14 - Multiplexers

Lecture 15 - Multiplexers based Circuit Design

Lecture 16 - Design Process and Verilog

Lecture 17 - Demonstration of Verilog

Lecture 18 - Sequential Elements

Lecture 19 - Gated Latches

Lecture 20 - Flip Flops

Lecture 21 - Verilog Demonstration: Assign Statement and Instantiation

Lecture 22 - Sequential Circuits

Lecture 23 - Logic Gates and Electrical Properties

Lecture 24 - Delays

Lecture 25 - Sequential Element Delays

Lecture 26 - More Sequential Circuits

Lecture 27 - Instruction to State Machines

Lecture 28 - Always Statement plus Mixing Styles in Verilog

Lecture 29 - State Machines: Sequential Logic Synthesis

Lecture 30 - State Machines: FSM Design Problems

Lecture 31 - State Machines: State Minimization

Lecture 32 - State Machines: State Assignment

Lecture 33 - State Machines: Timing Sequential Circuits

Lecture 34 - Verilog: Sequential Elements

Lecture 35 - Design of GCD Machine and Verilog Implementation

Lecture 36 - GCD Datapath and Controller

Lecture 37 - GCD State Machine

Lecture 38 - GCD Top Level Module plus Datapath

Lecture 39 - Datapath in Verilog

Lecture 40 - Datapath Elements for GCD

Lecture 41 - GCD State Machine in Verilog

Lecture 42 - GCD Testbench

Lecture 43 - Pipelining

Lecture 44 - Pipelining Technology and Methodology

Lecture 45 - Interleaving and Parallelism

Lecture 46 - Verilog Modeling (Assignment Statements)

Lecture 47 - Modeling Circuits with Pipelining

Lecture 48 - Signed Number Representation

Lecture 49 - Addition and Subtraction in 1's and 2's Complement Form

Lecture 50 - Ripple Carry Adder

Lecture 51 - Fast Adder

Lecture 52 - Multipliers and Other Circuits

Lecture 53 - Closing Remarks