InfoCoBuild

Computer Architecture

Computer Architecture. Instructor: Prof. Anshul Kumar, Department of Computer Science and Engineering, IIT Delhi. The aim of this course is to learn how computers work, the basic principles common across all computers, how to analyze their performance, how computers are designed and built, and issues affecting modern processors such as caches and pipelines. Topics covered in the lectures include: history of computers, instruction set architecture, performance evaluation of processors, ALU design, multiplier design, divider design, floating point arithmetic, processor design, pipelined processor design, memory hierarchy, and input/output subsystem. (from nptel.ac.in)

Lecture 26 - Pipelined Processor Design: Handling Data Hazards

Go to the Course Home or watch other lectures:

Lecture 01 - Introduction to Computer Architecture

Lecture 02 - History of Computers

Lecture 03 - Instruction Set Architecture I

Lecture 04 - Instruction Set Architecture II

Lecture 05 - Instruction Set Architecture III

Lecture 06 - Recursive Programs

Lecture 07 - Architecture Space: Features of MIPS ISA, RISC and CISC

Lecture 08 - Architecture Examples: PowerPC, SPARC, VAX, Intel x86

Lecture 09 - Performance and Cost

Lecture 10 - Performance Evaluation of Processors

Lecture 11 - Binary Arithmetic, ALU Design

Lecture 12 - ALU Design, Overflow

Lecture 13 - Multiplier Design

Lecture 14 - Divider Design

Lecture 15 - Fast Addition, Multiplication

Lecture 16 - Floating Point Arithmetic

Lecture 17 - Processor Design: Introduction

Lecture 18 - Processor Design: Simple Design

Lecture 19 - Processor Design: Simple Design (cont.)

Lecture 20 - Processor Design: Multi Cycle Approach

Lecture 21 - Processor Design: Control for Multi Cycle

Lecture 22 - Processor Design: Microprogrammed Control

Lecture 23 - Processor Design: Exception Handling

Lecture 24 - Pipelined Processor Design: Basic Idea

Lecture 25 - Pipelined Processor Design: Data Path and Control

Lecture 26 - Pipelined Processor Design: Handling Data Hazards

Lecture 27 - Pipelined Processor Design: Handling Control Hazards

Lecture 28 - Memory Hierarchy: Basic Idea

Lecture 29 - Memory Hierarchy: Cache Organization

Lecture 30 - Memory Hierarchy: Cache Organization (cont.)

Lecture 31 - Memory Hierarchy: Virtual Memory

Lecture 32 - Memory Hierarchy: Virtual Memory (cont.)

Lecture 33 - Input/Output Subsystem: Introduction

Lecture 34 - Input/Output Subsystem: Interfaces and Buses

Lecture 35 - Input/Output Subsystem: Interfaces and Buses (cont.)

Lecture 36 - Input/Output Subsystem: I/O Operations

Lecture 37 - Input/Output Subsystem: Designing I/O Systems

Lecture 38 - Concluding Remarks